View M36WT864TF_319297.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M36WT864TF M36WT864BF
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512K x16) SRAM, Multiple Memory Product
PRODUCT PREVIEW
FEATURES SUMMARY s SUPPLY VOLTAGE - VDDF = 1.65V to 2.2V - VDDS = VDDQF = 2.7V to 3.3V - VPPF = 12V for Fast Program (optional)
s s s
s s s s s s
SRAM 8 Mbit (512K x 16 bit) EQUAL CYCLE and ACCESS TIMES: 70ns LOW STANDBY CURRENT LOW VDDS DATA RETENTION: 1.5V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
ACCESS TIME: 70, 85, 100ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code, M36WT864TF: 8810h - Bottom Device Code, M36WT864BF: 8811h
Figure 1. Packages
s
FLASH MEMORY PROGRAMMING TIME - 8s by Word typical for Fast Factory Program - Double/Quadruple Word Program option - Enhanced Factory Program options
FBGA
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MEMORY BLOCKS - Multiple Bank Memory Array: 4 Mbit Banks - Parameter Blocks (Top or Bottom location)
Stacked LFBGA96 (ZA) 8 x 14mm
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DUAL OPERATIONS - Program Erase in one Bank while Read in others - No delay between Read and Write operations
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BLOCK LOCKING - All blocks locked at Power up - Any combination of blocks can be locked - WP for Block Lock-Down
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SECURITY - 128 bit user programmable OTP cells - 64 bit unique device number - One parameter block permanently lockable
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COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs (A19-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Clock (KF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Wait (WAITF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDDF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VDDQF and VDDS Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSF ,VSSQF and VSSS Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SRAM Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5. Flash Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FLASH BUS OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Read. . . . . . . . Bus Write. . . . . . . . Address Latch.. . . . Output Disable. . . . Standby. . . . . . . . . Reset. . . . . . . . . . . ...... ...... ...... ...... ...... ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FLASH COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Flash Standard Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . 22 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . 23 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program and Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Flash Factory Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FLASH STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VPPF Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8. Flash Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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FLASH CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Wait Polarity Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. Flash Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 7. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 8. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FLASH READ MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . 36 Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FLASH BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Reading a Block's Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 13. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES. . . . . . . . . . . . . . . . . . . . . . . 39 Table 14. Flash Program, Erase Times and Endurance Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 18. Flash DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 19. Flash DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 20. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 11. Flash Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 45 Figure 12. Flash Asynchronous Page Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 21. Flash Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 13. Flash Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 14. Flash Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 15. Flash Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 22. Flash Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 16. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 23. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 17. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 24. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 18. Flash Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 25. Flash Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 19. SRAM Address Controlled, Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms . . . . . . . . . . . . 56 Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms . . . . . . . . . . . . . 57 Table 26. SRAM Read and Standby AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 22. SRAM Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 24. SRAM Write AC Waveforms, UB/LB Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 27. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 25. SRAM Low VDD Data Retention AC Waveforms, E1S Controlled. . . . . . . . . . . . . . . . . 61 Figure 26. SRAM Low VDD Data Retention AC Waveforms, E2S Controlled. . . . . . . . . . . . . . . . . 61 Table 28. SRAM Low VDD Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline 62 Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data 62 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 30. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 APPENDIX A. FLASH BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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Table 32. Flash Top Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 33. Flash Bottom Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 APPENDIX B. FLASH COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 34. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 35. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 36. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 37. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 39. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 40. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 41. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 42. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 43. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 28. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 29. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 30. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 31. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 79 Figure 32. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 34. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 35. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 83 Figure 36. Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 37. Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 44. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45. Command Interface States - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 46. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 47. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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SUMMARY DESCRIPTION The M36WT864 is a low voltage Multiple Memory Product which combines two memory devices; a 64 Mbit Multiple Bank Flash memory and an 8 Mbit SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be active at the same time. The memory is offered in a Stacked LFBGA96 (8 x 14mm, 0.8 mm pitch) package and is supplied with all the bits erased (set to `1'). Figure 2. Logic Diagram
Table 1. Signal Names
A0-A18 A19-A21 DQ0-DQ15 VDDF VDDQF VPPF VSSF VSSQF Address Inputs Address Inputs for Flash Chip only Data Input/Output Flash Power Supply Flash Power Supply for I/O Buffers Flash Optional Supply Voltage for Fast Program & Erase Flash Ground Flash Ground for I/O Buffers SRAM Power Supply SRAM Ground Not Connected Internally Do Not Use as Internally Connected
VDDQF VDDF 22 A0-A21 EF GF WF RPF WPF LF KF E1S E2S GS WS UBS LBS VSSF
VDDS
VPPF 16 DQ0-DQ15
VDDS VSSS NC DU
WAITF
Flash control functions LF Latch Enable input Chip Enable input Output Enable input Write Enable input Reset input Write Protect input Flash Burst Clock Wait Data in Burst Mode
M36WT864TF M36WT864BF
EF GF WF RPF WPF KF WAITF
SRAM control functions
VSSS
E1S, E2S GS
AI06270
Chip Enable inputs Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input
VSSQF
WS UBS LBS
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M36WT864TF, M36WT864BF
Figure 3. LFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8
#A
NC
NC
NC
NC
#B
NC
NC
NC
NC
A
A4
A18
A19
VSSS
WS
KF
A21
A11
B
A5
LBS
NC
VSSS
E2S
VDDS
NC
A12
C
A3
A17
NC
VPPF
VDDF
VSSF
A9
A13
D
A2
A7
NC
WPF
LF
A20
A10
A15
E
A1
A6
UBS
RP
WF
A8
A14
A16
F
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAITF
DU
G
GS
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
DU
H
E1S
GF
DQ9
DQ11
DQ4
DQ6
DQ15
DU
J
EF
DU
DU
VDDS
VDDS
DU
VDDQF
VSSS
K
VSSS
VSSQF
VDDQF
VDDF
VSSS
VSSQF
VSSF
VSSS
#C
NC
NC
NC
NC
#D
NC
NC
NC
NC
AI06271
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SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A18). Addresses A0-A18 are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals, while the SRAM is accessed through two Chip Enable signals (E1S and E2S) and the Write Enable signal (WS). Address Inputs (A19-A21). Addresses A19-A21 are inputs for the Flash component only. The Flash memory is accessed through the Chip Enable (EF) and Write Enable (WF) signals. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Flash Output Enable (GF). The Output Enable controls data outputs during the Bus Read operation of the memory. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Status). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 2, DC Characteristics - Currents for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset.
When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 19, DC Characteristics). Flash Latch Enable (LF). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Flash Clock (KF). The clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous read and in write operations. Flash Wait (WAITF). Wait is a Flash output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs activate the SRAM memory control logic, input buffers and decoders. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while WS remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array. WS is active low. SRAM Output Enable (GS). The Output Enable gates the outputs through the data buffers during a read operation of the SRAM memory. GS is active low. SRAM Upper Byte Enable (UBS). The Upper Byte Enable input enables the upper byte for SRAM (DQ8-DQ15). UBS is active low. SRAM Lower Byte Enable (LBS). The Lower Byte Enable input enables the lower byte for SRAM (DQ0-DQ7). LBS is active low. VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory de-
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vice. It is the main power supply for all Flash operations (Read, Program and Erase). VDDQF and VDDS Supply Voltage. VDDQF provides the power supply for the Flash memory I/O pins and VDDS provides the power supply for the SRAM control and I/O pins. This allows all Outputs to be powered independently from the Flash core power supply, VDDF. VDDQF can be tied to VDDS or it can use a separate supply. VPPF Program Supply Voltage. VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against program or erase, while VPPF > VPP1F enables these functions (see Tables 18 and 19, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSSF ,VSSQF and VSSS Grounds. VSSF, VSSQF and VSSS are the ground references for all voltage measurements in the Flash (core and I/O Buffers) and SRAM chips, respectively. Note: Each device in a system should have VDDF and VPPF decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 10, AC Measurement Load Circuit. The PCB trace widths should be sufficient to carry the required VPPF program and erase currents.
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M36WT864TF, M36WT864BF
FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. Recommended operating conditions do not allow both the Flash and the SRAM to be in active mode at the same time. The most common example is Figure 4. Functional Block Diagram
simultaneous read operations on the Flash and the SRAM which would result in a data bus contention. Therefore it is recommended to put the SRAM in the high impedance state when reading the Flash and vice versa (see Table 2 Main Operation Modes for details).
VDDF VDDQF VPPF
EF GF WF RPF WPF LF WAITF KF A19-A21 A0-A18 Flash Memory 64 Mbit (x16)
VDDS
VSSQF VSSF
DQ0-DQ15
E1S E2S GS WS UBS LBS SRAM 8 Mbit (x 16)
VSSS
AI06272
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M36WT864TF, M36WT864BF
Table 2. Main Operation Modes
Operation Mode Bus Read Bus Write Flash Memory Address Latch Output Disable Standby Reset Read Write EF VIL VIL VIL VIL VIH X GF VIL VIH X VIH X X WF VIH VIL VIH VIH X X LF VIL(2) VIL(2) VIL X X X RPF VIH VIH VIH VIH VIH VIL Hi-Z Hi-Z VIL VIL VIH SRAM Standby/ Power Down Any Flash mode is allowable X X Data Retention Output Disable
Note: 1. 2. 3. 4.
WAITF
E1S
E2S
GS
WS
UBS, LBS
DQ15-DQ0 Data Output Data Input Data Output or Hi-Z (3) Hi-Z Hi-Z Hi-Z Data out Word Read Data in Word Write Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
SRAM must be disabled SRAM must be disabled SRAM must be disabled SRAM must be disabled Any SRAM mode is allowed Any SRAM mode is allowed VIH VIH X VIL X VIL VIH VIL X X X X X VIH VIH VIL X X X X VIH VIL VIL X X VIH X X
Flash must be disabled Flash must be disabled
Any Flash mode is allowable
VIH VIL
Any Flash mode is allowable
X = Don't care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command.
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M36WT864TF, M36WT864BF
Flash Memory Component The Flash memory is a 64 Mbit (4Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V VDD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPPF power supply is provided to speed up customer programming. The device features an asymmetrical block architecture with an array of 135 blocks divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 3, and the memory maps are shown in Figure 5. The Parameter Blocks are located at the top of the memory address space for the M36WT864TF, and at the bottom for the M36WT864BF. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The device features an Automatic Standby mode. During asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPPF VPPLK all blocks are protected against program or erase. All blocks are locked at Power- Up. The device includes a Protection Register and a Security Block to increase the protection of a system's design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 6, shows the Security Block and Protection Register Memory Map. SRAM Component The SRAM is an 8 Mbit (512Kb x16) asynchronous random access memory which features a super low voltage operation and low current consumption with an access time of 70ns. The memory operations can be performed using a single low voltage supply, 2.7V to 3.3V.
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M36WT864TF, M36WT864BF
Table 3. Flash Bank Architecture
Number Parameter Bank Bank 0 Bank 1 Bank 2 ---Bank Size 4 Mbits 4 Mbits 4 Mbits 4 Mbits ---Parameter Blocks 8 blocks of 4 KWords ---Main Blocks 7 blocks of 32 KWords 8 blocks of 32 KWords 8 blocks of 32 KWords 8 blocks of 32 KWords ---8 blocks of 32 KWords 8 blocks of 32 KWords
Bottom Boot Block Address lines A21-A0 000000h 000FFFh 007000h 007FFFh 008000h 00FFFFh 038000h 03FFFFh 040000h 047FFFh Bank 0 078000h 07FFFFh 080000h 087FFFh Bank 1 0B8000h 0BFFFFh 0C0000h 0C7FFFh Bank 2 0F8000h 0FFFFFh 7 Main Blocks 32 KWord 4 KWord 8 Parameter Blocks 4 KWord Bank 14 3F8000h 3FFFFFh 32 KWord 3C0000h 3C7FFFh 32 KWord 8 Main Blocks 32 KWord 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 4 KWord 8 Parameter Blocks 4KWord 32 KWord 7 Main Blocks 32 KWord 32 KWord 8 Main Blocks
Bank 13 Bank 14
4 Mbits 4 Mbits
-
Figure 5. Flash Block Addresses
Top Boot Block Address lines A21-A0 000000h 007FFFh Bank 14 038000h 03FFFFh 32 KWord 32 KWord 8 Main Blocks Parameter Bank
300000h 307FFFh Bank 2 338000h 33FFFFh 340000h 377FFFh Bank 1 378000h 37FFFFh 380000h 387FFFh Bank 0 3D8000h 3BFFFFh 3C0000h 3C7FFFh 3F0000h 3F7FFFh 3F8000h 3F8FFFh 3FF000h 3FFFFFh
32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord
Parameter Bank
AI06273
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M36WT864TF, M36WT864BF
FLASH BUS OPERATIONS There are six standard bus operations that control the Flash device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 2, Main Operating Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 11, 12, 13 and 14 Read AC Waveforms, and Tables 21 and 22 Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the bus write operation. See Figures 16 and 17, Write AC Waveforms, and Tables 23 and 24, Write AC Characteristics, for details of the timing requirements. Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. Output Disable. The outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset are at VIH. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
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FLASH COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands will reset the device to read mode. Refer to Table 4, Command Codes and Appendix D, Tables 44, 45, 46 and 47, Command Interface States - Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command.
Table 4. Command Codes
Hex Code 01h 03h 10h 20h 2Fh 30h 35h 40h 50h 56h 60h 70h 75h 80h 90h 98h B0h C0h Command Block Lock Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Block Lock-Down Confirm Enhanced Factory Program Setup Double Word Program Setup Program Setup Clear Status Register Quadruple Word Program Setup Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup Read Status Register Quadruple Enhanced Factory Program Setup Bank Erase Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Protection Register Program Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block Unlock Confirm or Enhanced Factory Program Confirm Read Array
D0h
FFh
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COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands Read CFI Query Command used to read, write to and configure the device. The Read CFI Query command is used to read Refer to Table 5, Standard Commands, in condata from the Common Flash Interface (CFI). The junction with the following text descriptions. Read CFI Query Command consists of one Bus Read Array Command Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus The Read Array command returns the addressed Read operations in the same bank read from the bank to Read Array mode. One Bus Write cycle is Common Flash Interface. required to issue the Read Array command and return the addressed bank to Read Array mode. If a Read CFI Query command is issued in a bank Subsequent read operations will read the adthat is executing a Program or Erase operation the dressed location and output the data. A Read Arbank will go into Read CFI Query mode, subseray command can be issued in one bank while quent Bus Read cycles will output the CFI data programming or erasing in another bank. However and the Program/Erase controller will continue to if a Read Array command is issued to a bank curProgram or Erase in the background. This mode rently executing a Program or Erase operation the supports asynchronous or single synchronous command will be executed but the output data is reads only, it does not support page mode or synnot guaranteed. chronous burst reads. Read Status Register Command The status of the other banks is not affected by the command (see Table 11). After issuing a Read The Status Register indicates when a Program or CFI Query command, a Read Array command Erase operation is complete and the success or should be issued to the addressed bank to return failure of operation itself. Issue a Read Status the bank to Read Array mode. Register command to read the Status Register See Appendix C, Common Flash Interface, Tables content. The Read Status Register command can 34, 35, 36, 37, 38, 40, 41, 42 and 43 for details on be issued at any time, even during Program or the information contained in the Common Flash InErase operations. terface memory area. The following read operations output the content Clear Status Register Command of the Status Register of the addressed bank. The Status Register is latched on the falling edge of E The Clear Status Register command can be used or G signals, and can be read until E or G returns to reset (set to `0') error bits 1, 3, 4 and 5 in the Stato VIH. Either E or G must be toggled to update the tus Register. One bus write cycle is required to islatched data. See Table 8 for the description of the sue the Clear Status Register command. After the Status Register Bits. This mode supports asynClear Status Register command the bank returns chronous or single synchronous reads only. to read mode. Read Electronic Signature Command The error bits in the Status Register do not autoThe Read Electronic Signature command reads matically return to `0' when a new command is isthe Manufacturer and Device Codes, the Block sued. The error bits in the Status Register should Locking Status, the Protection Register, and the be cleared before attempting a new Program or Configuration Register. Erase command. The Read Electronic Signature command consists Block Erase Command of one write cycle to an address within one of the The Block Erase command can be used to erase banks. A subsequent Read operation in the same a block. It sets all the bits within the selected block bank will output the Manufacturer Code, the Deto '1'. All previous data in the block is lost. If the vice Code, the protection Status of the blocks in block is protected then the Erase operation will the targeted bank, the Protection Register, or the abort, the data in the block will not be changed and Configuration Register (see Table 6). the Status Register will output the error. The Block If a Read Electronic Signature command is issued Erase command can be issued at any moment, rein a bank that is executing a Program or Erase opgardless of whether the block has been proeration the bank will go into Read Electronic Siggrammed or not. nature mode, subsequent Bus Read cycles will Two Bus Write cycles are required to issue the output the Electronic Signature data and the Procommand. gram/Erase controller will continue to program or s The first bus cycle sets up the Erase command. erase in the background. This mode supports s The second latches the block address in the asynchronous or single synchronous reads only, it internal state machine and starts the Program/ does not support page mode or synchronous burst Erase Controller. reads.
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If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits 4 and 5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 32, Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Bank Erase Command The Bank Erase command can be used to erase a bank. It sets all the bits within the selected bank to '1'. All previous data in the bank is lost. The Bank Erase command will ignore any protected blocks within the bank. If all blocks in the bank are protected then the Bank Erase operation will abort and the data in the bank will not be changed. The Status Register will not output any error. Two Bus Write cycles are required to issue the command. s The first bus cycle sets up the Bank Erase command. s The second latches the bank address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Bank Erase Confirm (D0h), Status Register bits SR4 and SR5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the bank must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Bank Erase operations the bank being erased will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. A Bank Erase operation cannot be suspended. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Program Command The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles are required to issue the Program Command. s The first bus cycle sets up the Program command. s The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 28, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to `1'. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the suspended block), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block LockDown or Block Unlock commands will also be accepted. The block being erased may be protected
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by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 31, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 33, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the programming operation then read the array. See Appendix C, Figure 31, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 33, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to `1'. The user can only program the bits to `0'. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register also protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter Block #0 (see Figure 6, Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. See Appendix C, Figure 35, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command. The Set Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. s The first cycle writes the setup command and the address corresponding to the Configuration Register content. s The second cycle writes the Configuration Register data and the confirm command. Once the command is issued the memory returns to Read mode. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command.
s
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The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 34, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. s The first bus cycle sets up the Block Unlock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 34, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A lockeddown block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. s The first bus cycle sets up the Block Lock command. s The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 13 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 34, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command.
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Table 5. Flash Standard Commands
Cycles Bus Operations 1st Cycle Op.
Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
Commands
2nd Cycle Data
FFh 70h 90h 98h 50h 20h 80h 40h or 10h B0h D0h C0h 60h 60h 60h 60h Write Write Write Write Write Write Write Write BA BKA WA D0h D0h PD
Add
BKA BKA BKA BKA BKA BKA BKA BKA X X PRA CRD BKA BKA BKA
Op.
Read Read Read Read
Add
WA BKA(2) BKA(2) BKA(2)
Data
RD SRD ESD QD
Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Bank Erase Program Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Lock Block Unlock Block Lock-Down
1+ 1+ 1+ 1+ 1 2 2 2 1 1 2 2 2 2 2
PRA CRD BA BA BA
PRD 03h 01h D0h 2Fh
Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.
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Table 6. Electronic Signature Codes
Code Manufacturer Code Top Device Code Bottom Lock Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Security Block Permanently Locked Protection Register Lock OTP Area Permanently Locked Security Block and OTP Area Permanently Locked Bank Address + 81 Bank Address + 84 Protection Register Bank Address + 85 Bank Address + 8C
Note: CR=Configuration Register.
Address (h) Bank Address + 00 Bank Address + 01 Bank Address + 01
Data (h) 0020 8810 8811 0001 0000
Block Address + 02 0003 0002 Bank Address + 03 Bank Address + 05 Reserved CR 0006 0002 Bank Address + 80 0004 0000 Unique Device Number OTP Area
Figure 6. Flash Security Block and Protection Register Memory Map
PROTECTION REGISTER 8Ch SECURITY BLOCK 85h 84h Parameter Block # 0 81h 80h Protection Register Lock 2 1 0 Unique device number User Programmable OTP
AI06181
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COMMAND INTERFACE - FACTORY PROGRAM COMMANDS Five bus write cycles are necessary to issue the The Factory Program commands are used to Quadruple Word Program command. speed up programming. They require V PPF to be at VPPH. Refer to Table 7, Factory Program Coms The first bus cycle sets up the Double Word mands, in conjunction with the following text deProgram Command. scriptions. s The second bus cycle latches the Address and Double Word Program Command the Data of the first word to be written. The Double Word Program command improves s The third bus cycle latches the Address and the the programming throughput by writing a page of Data of the second word to be written. two adjacent words in parallel. The two words s The fourth bus cycle latches the Address and must differ only for the address A0. the Data of the third word to be written. Programming should not be attempted when VPPF s The fifth bus cycle latches the Address and the is not at VPPH. The command can be executed if Data of the fourth word to be written and starts VPPF is below VPPH but the result is not guaranthe Program/Erase Controller. teed. Read operations to the bank being programmed Three bus write cycles are necessary to issue the output the Status Register content after the proDouble Word Program command. gramming has started. s The first bus cycle sets up the Double Word Programming aborts if Reset goes to VIL. As data Program Command. integrity cannot be guaranteed when the program s The second bus cycle latches the Address and operation is aborted, the memory locations must the Data of the first word to be written. be reprogrammed. s The third bus cycle latches the Address and the During Quadruple Word Program operations the Data of the second word to be written and starts bank being programmed will only accept the Read the Program/Erase Controller. Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other Read operations in the bank being programmed commands will be ignored. output the Status Register content after the programming has started. Dual operations are not supported during Quadruple Word Program operations and it is not recomDuring Double Word Program operations the bank mended to suspend a Quadruple Word Program being programmed will only accept the Read Aroperation. Typical Program times are given in Taray, Read Status Register, Read Electronic Signable 14, Program, Erase Times and Program/Erase ture and Read CFI Query command, all other Endurance Cycles. commands will be ignored. Dual operations are not supported during Double Word Program operSee Appendix C, Figure 30, Quadruple Word Proations and it is not recommended to suspend a gram Flowchart and Pseudo Code, for the flowDouble Word Program operation. Typical Program chart for using the Quadruple Word Program times are given in Table 14, Program, Erase command. Times and Program/Erase Endurance Cycles. Enhanced Factory Program Command Programming aborts if Reset goes to VIL. As data The Enhanced Factory Program command can be integrity cannot be guaranteed when the program used to program large streams of data within any operation is aborted, the memory locations must one block. It greatly reduces the total programbe reprogrammed. ming time when a large number of Words are writSee Appendix C, Figure 29, Double Word Proten to a block at any one time. gram Flowchart and Pseudo Code, for the flowThe use of the Enhanced Factory Program comchart for using the Double Word Program mand requires certain operating conditions. command. s VPPF must be set to VPPH Quadruple Word Program Command s VDD must be within operating range The Quadruple Word Program command ims Ambient temperature, TA must be 25C 5C proves the programming throughput by writing a page of four adjacent words in parallel. The four s The targeted block must be unlocked words must differ only for the addresses A0 and Dual operations are not supported during the EnA1. hanced Factory Program operation and the comProgramming should not be attempted when VPPF mand cannot be suspended. is not at VPPH. The command can be executed if For optimum performance the Enhanced Factory VPPF is below VPPH but the result is not guaranProgram commands should be limited to a maxiteed. mum of 10 program/erase cycles per block. If this
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limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 14. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 7, Enhanced Factory Program Command and Figure 36, Enhanced Factory Program Flowchart. Setup Phase. The Enhanced Factory Program command requires two Bus Write operations to initiate the command. s The first bus cycle sets up the Enhanced Factory Program command. s The second bus cycle confirms the command. The Status Register P/E.C. Bit 7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 7, Enhanced Factory Program Command and Figure 36, Enhanced Factory Program Flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word. 2. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory returns to the Read mode. If the Program/ Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register. Exit Phase. Status Register P/E.C. bit SR7 set to `1' indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. Quadruple Enhanced Factory Program Command The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent words in parallel. The four words must differ only for the addresses A0 and A1. VPPF must be set to VPPH during Quadruple Enhanced Factory Program. It has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block.
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Setup Phase. The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. Load Phase. The Load Phase requires 4 cycles to load the data (refer to Table 7, Factory Program Commands and Figure 37, Quadruple Enhanced Factory Program Flowchart). Once the first Word of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit 7 set to `0'). This check is not required for subsequent Load Phases. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. The memory is now set to enter the Program and Verify Phase. Program and Verify Phase. In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to `0', and that the device is not waiting for new data, Status Register bit SR0 set to `1'. When Status Register bit SR0 is set to `0' the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed. Exit Phase. Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register. Status Register bit SR7 set to `1' and bit 0 set to `0' indicate that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details.
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Table 7. Flash Factory Program Commands
Cycles Bus Write Operations 1st Add
Double Word Program(4) Quadruple Word Program(5) 3 5
Command
Phase
2nd Data 35h 56h Add WA1 WA1 Data PD1 PD1
3rd Add WA2 WA2 Data PD2 PD2
Final -1 Add Data
Final Add Data
BKA BKA
WA3
PD3
WA4
PD4
Enhanced Factory Program
(6)
Setup, Program Verify, Exit Setup, first Load First Program & Verify Subsequent Loads Subsequent Program & Verify Exit
2 +n +1
BKA
30h
BA
D0h
WA1(2)
PD1
WAn(3)
PAn
NOT FFFFh WA1(2) NOT FFFFh WA1(2) WA4(7) PD4
n (2) +1 WA1
5
PD1 75h
WA2(3) WA1(2)
PD2 WA3(3) PD1 WA2(7)
PD3 PD2
WAn(3) WA3(7)
PAn PD3
BKA
Automatic WA1i
(2)
Quadruple Enhanced Factory Program
(5,6)
4
PD1i
WA2i
(7)
PD2i
WA3i
(7)
PD3i
WA4i
(7)
PD4i
Automatic NOT WA1
(2)
1
FFFFh
Note: 1. 2. 3. 4. 5. 6.
WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1. Address can remain Starting Address WA1 or be incremented. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed. 7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address.
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FLASH STATUS REGISTER The Flash memory contains a Status Register which provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to `0'), the Program/Erase Controller is active; when the bit is High (set to `1'), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPPF Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an Erase opera-
tion has been suspended or is going to be suspended in the addressed block. When the Erase Suspend Status bit is High (set to `1'), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify a Program failure. When the Program Status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPPF Status Bit (SR3). The VPPF Status bit can be used to identify an invalid voltage on the VPPF pin during Program and Erase operations. The VPPF pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPPF becomes invalid during an operation. When the VPPF Status bit is Low (set to `0'), the voltage on the VPPF pin was sampled at a valid voltage; when the VPPF Status bit is High (set to `1'), the VPPF pin has a voltage that is below the
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VPPF Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPPF Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to `1'), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0). The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to `0'), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to `0') and the Bank Write Status bit is High (set to `1'), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to `0'), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to `1') the device is not ready for the next Word. Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register.
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Table 8. Flash Status Register Bits
Bit SR7 Name P/E.C. Status Type Status '0' '1' SR6 Erase Suspend Status Status '0' '1' SR5 Erase Status Error '0' '1' SR4 Program Status Error '0' '1' SR3 VPPF Status Error '0' '1' SR2 Program Suspend Status Status '0' '1' SR1 Block Protection Status Error '0' '0' SR7 = `1' No Program or erase operation in the device Bank Write Status Status SR7 = `0' '1' SR0 Multiple Word Program Status (Enhanced Factory Program mode) '1' SR7 = `1' Not Allowed Status SR7 = `0' '0' SR7 = `1' the device is exiting from EFP
Note: Logic level '1' is High, '0' is Low.
Logic Level '1' Ready Busy Erase Suspended
Definition
Erase In progress or Completed Erase Error Erase Success Program Error Program Success VPPF Invalid, Abort VPPF OK Program Suspended Program In Progress or Completed Program/Erase on protected Block, Abort No operation to protected blocks SR7 = `0' Program or erase operation in addressed bank
Program or erase operation in a bank other than the addressed bank
SR7 = `1' Not Allowed SR7 = `0' the device is NOT ready for the next word
the device is ready for the next Word
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FLASH CONFIGURATION REGISTER The Flash memory contains a Configuration Register which is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 7 and 8 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', read operations are asynchronous; when the Read Select bit is set to '0', read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to'1' for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 9, Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or tDELAY is supplied either one of the following two equations must be satisfied: (n + 1) tK tACC - tAVK_CPU + tQVK_CPU (n + 2) tK tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last tDELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device.
Refer to Figure 7, X-Latency and Data Output Configuration Example. Wait Polarity Bit (CR10) In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High (default). Data Output Configuration Bit (CR9) The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is '0' the output data is valid for one clock cycle, when the Data Output Configuration Bit is '1' the output data is valid for two clock cycles. The Data Output Configuration depends on the condition: s tK > tKQV + tQVK_CPU where tK is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 7, X-Latency and Data Output Configuration Example. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When the Wait bit is '0' the Wait output pin is asserted during the wait state. When the Wait bit is '1' (default) the Wait output pin is asserted one clock cycle before the wait state. WAIT is asserted during a continuous burst and also during a 4 or 8 burst length if no-wrap configuration is selected. WAIT is not asserted during asynchronous reads, single synchronous reads or during latency in synchronous reads. Burst Type Bit (CR7) The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' (default) the memory outputs from sequential addresses. See Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is
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the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device asserts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR5 and CR4 are reserved for future use.
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Table 9. Flash Configuration Register
Bit CR15 CR14 010 011 100 CR13-CR11 X-Latency 101 111 5 clock latency Reserved Description 0 Read Select 1 Asynchronous Read (Default at power-on) Reserved 2 clock latency 3 clock latency 4 clock latency Value Synchronous Read Description
Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 0 CR3 Wrap Burst 1 001 CR2-CR0 Burst Length 010 111 No Wrap 4 words 8 words Continuous (CR7 must be set to `1') Valid Clock Edge 1 Rising Clock edge Reserved Wrap Sequential (default) Falling Clock edge WAIT is active one data cycle before wait state (default) Interleaved 0 1 0 CR8 WAIT is active high (default) Data held for one clock cycle Data held for two clock cycles WAIT is active during wait state WAIT is active Low
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Table 10. Burst Type Definition
Mode Start Address 4 Words Sequential 0 1 2 3 ... Wrap 7 ... 60 61 62 63 Sequential 0 1 2 3 ... No-wrap 7 ... 60 61 62 63 60-61-62-63 61-62-63-WAIT-64 62-63-WAITWAIT-64-65 63-WAIT-WAITWAIT-64-65-66 60-61-62-63-64-65-6667 61-62-63-WAIT-64-6566-67-68 62-63-WAIT-WAIT-6465-66-67-68-69 63-WAIT-WAIT-WAIT64-65-66-67-68-69-70 7-8-9-10 7-8-9-10-11-12-13-14 Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst ) 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 Interleaved Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9... 3-4-5-6-7-8-9-10 Interleaved 60-61-62-63-64-65-66... 61-62-63-WAIT-64-65-66... 62-63-WAIT-WAIT-64-65-66... 63-WAIT-WAIT-WAIT-64-6566... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 Words Continuous Burst Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9...
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Figure 7. X-Latency and Data Output Configuration Example
X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle
E
L
A21-A0 tDELAY
VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU
DQ15-DQ0 VALID DATA VALID DATA
Note. Settings shown: X-latency = 4, Data Output held for one clock cycle
AI06182
Figure 8. Wait Configuration Example
E
K
L
A21-A0
VALID ADDRESS
DQ15-DQ0
VALID DATA VALID DATA
NOT VALID
VALID DATA
WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1'
AI06972
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FLASH READ MODES Flash Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for Asynchronous operations. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode. The first read operation within the Page has a longer access time (Tacc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. See Table 21, Asynchronous Read AC Characteristics, Figure 11, Asynchronous Random Access Read AC Waveform and Figure 12, Asynchronous Page Read AC Waveform for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to a 4 Word Page the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X latency and the Wait state and is only deasserted when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 64 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst Read mode, in other modes, WAIT is always asserted (except for Read Array mode). See Table 22, Synchronous Read AC Characteristics and Figure 13, Synchronous Burst Read AC Waveform for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Other Configuration Register parameters have no effect on Single Synchronous Read operations.
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Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always asserted. See Table 22, Synchronous Read AC Characteristics and Figure 14, Single Synchronous Read AC Waveform for details.
FLASH DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE then a Program command can be issued to anothThe Multiple Bank Architecture of the Flash memer block, so the device can have one block in ory provides flexibility for software developers by Erase Suspend mode, one programming and othallowing code and data to be split with 4Mbit graner banks in Read mode. Bus Read operations are ularity. The Dual Operations feature simplifies the allowed in another bank between setup and consoftware management of the device and allows firm cycles of program or erase operations. The code to be executed from one bank while another combination of these features means that read opbank is being programmed or erased. erations are possible at any moment. The Dual operations feature means that while programming or erasing in one bank, Read operaTables 11 and 12 show the dual operations possitions are possible in another bank with zero ble in other banks and in the same bank. Note that latency (only one bank at a time is allowed to be in only the commonly used commands are repreProgram or Erase mode). If a Read operation is resented in these tables. For a complete list of posquired in a bank which is programming or erasing, sible commands refer to Appendix D, Command the Program or Erase operation can be suspendInterface State Tables. ed. Also if the suspended operation was Erase Table 11. Dual Operations Allowed In Other Banks
Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Status Register Yes Yes Yes Yes Yes Read CFI Query Yes Yes Yes Yes Yes Read Electronic Program Signature Yes Yes Yes Yes Yes Yes - - - Yes Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Table 12. Dual Operations Allowed In Same Bank
Commands allowed in same bank Status of bank Read Array Yes -(2) -(2) Yes(1) Yes(1) Read Read Read Status Electronic Program CFI Query Register Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - Yes(1) Erase Yes - - - - Program/ Program/ Erase Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes
Idle Programming Erasing Program Suspended Erase Suspended
Note: 1. Not allowed in the Block or Word that is being erased or programmed. 2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.
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FLASH BLOCK LOCKING The Flash memory features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. s Lock/Unlock - this first level allows softwareonly control of block locking.
s
Lock-Down - this second level requires hardware interaction before locking can be changed. VPPF VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
s
The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 34, shows a flowchart for the locking operations. Reading a Block's Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix , Command Interface State Table, for detailed information on which commands are valid during erase suspend.
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Table 13. Flash Lock Status
Current Protection Status(1) (WP, DQ1, DQ0) Current State 1,0,0 1,0,1(2) 1,1,0 1,1,1 0,0,0 0,0,1(2) 0,1,1 Program/Erase Allowed yes no yes no yes no no After Block Lock Command 1,0,1 1,0,1 1,1,1 1,1,1 0,0,1 0,0,1 0,1,1 Next Protection Status(1) (WP, DQ1, DQ0) After Block Unlock Command 1,0,0 1,0,0 1,1,0 1,1,0 0,0,0 0,0,0 0,1,1 After Block Lock-Down Command 1,1,1 1,1,1 1,1,1 1,1,1 0,1,1 0,1,1 0,1,1 After WP transition 0,0,0 0,0,1 0,1,1 0,1,1 1,0,0 1,0,1 1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (`1' for a locked-down block) and DQ0 (`1' for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
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M36WT864TF, M36WT864BF
FLASH PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of of Program/ Erase cycles depends on the voltage Program/ Erase cycles per block are shown in Tasupply used. ble 14. In the Flash memory the maximum number Table 14. Flash Program, Erase Times and Endurance Cycles
Parameter Parameter Block (4 KWord) Erase(2) Preprogrammed Main Block (32 KWord) Erase Not Preprogrammed Preprogrammed Bank (4Mbit) Erase Not Preprogrammed VPPF = VDD Parameter Block (4 KWord) Program(3) Main Block (32 KWord) Program(3) Word Program (3) Program Suspend Latency Erase Suspend Latency Main Blocks Program/Erase Cycles (per Block) Parameter Blocks Parameter Block (4 KWord) Erase Main Block (32 KWord) Erase Bank (4Mbit) Erase Bank (4Mbit) Program (Quad-Enhanced Factory Program) VPPF = VPPH 4Mbit Program Quadruple Word 100,000 0.3 0.9 3.5 t.b.a.(4) 510 8 8 32 64 256 1000 2500 100 2.5 4 cycles s s s s ms s ms ms ms ms cycles cycles 100,000 4.5 40 300 10 5 5 10 100 10 20 s ms ms s s s cycles 1.1 3 4 s s Condition Min Typ 0.3 0.8 Typical after 100k W/E Cycles 1 3 Max 2.5 4 Unit s s
Word/ Double Word/ Quadruple Word Program(3) Parameter Block (4 KWord) Program(3) Quadruple Word Word Quadruple Word Word Main Blocks Program/Erase Cycles (per Block) Parameter Blocks
Main Block (32 KWord) Program(3)
Note: 1. 2. 3. 4.
TA = -40 to 85C; VDD = 1.65V to 2.2V; VDDQ = 1.65V to 3.3V. The difference between Preprogrammed and not preprogrammed is not significant (30ms). Excludes the time needed to execute the command sequence. t.b.a. = to be announced
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M36WT864TF, M36WT864BF
SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The data is output either by x8 (DQ0-DQ7) or x16 (DQ0-DQ15) depending on which of the LBS and UBS signals are enabled. The SRAM is in Read mode whenever Chip Enable, E2S, and Write Enable, WS, are at VIH, and Output Enable, GS, and Chip Enable E1S are at VIL. Valid data will be available on the output pins after a time of tAVQV after the last stable address. If the Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tEHQV, or tGLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV (see Table 26, Figures 19 and 20). Write. Write operations are used to write data to the SRAM. The SRAM is in Write mode whenever Write Enable, WS, and Chip Enable, E1S, are at VIL, and Chip Enable, E2S, is at VIH. Either the Chip Enable input, E1S or the Write Enable input, WS, must be deasserted during address transitions for subsequent write cycles. A Write operation is initiated when E1S is at VIL, E2S is at VIH and WS is at VIL. When UBS or LBS are Low, the data is latched on the falling edge of E1S, or WS, whichever occurs first. When UBS or
LBS are High, the data is latched on the falling edge of UBS, or LBS , whichever occurs first. The Write cycle is terminated on the rising edge of E1S, WS , UBS or LBS, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH, GS=VIL and UBS=LBS=VIL), then WS will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. The Data input must be valid for tDVWH before the rising edge of Write Enable, for tDVEH before the rising edge of E1S or for tDVBH before the rising edge of UBS/ LBS, whichever occurs first, and remain valid for tWHDX, tEHDX and tBHDX respectively. (see Table 27, Figure 22, 23 and 24). Standby/Power-Down. The SRAM component has a chip enabled power-down feature which invokes an automatic standby mode (see Table 26, Figure 19). The SRAM is in Standby mode whenever either Chip Enable is deasserted, E1S at VIH or E2S at VIL. Data Retention. The SRAM data retention performances as VDDS go down to VDR are described in Table 28 and Figures 25 and 26. In E1S controlled data retention mode, the minimum standby current mode is entered when E1S VDDS - 0.2V and E2S 0.2V or E2S VDDS - 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S 0.2V. Output Disable. The SRAM is in the output disable state when GS and WS are both at VIH, refer to Table 2 for more details.
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M36WT864TF, M36WT864BF
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 15. Absolute Maximum Ratings
Value Symbol TA TBIAS TSTG VIO VDDF VDDQF / VDDS VPPF IO tVPPFH Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPPF at VPPFH Min -40 -40 -65 -0.5 -0.2 -0.2 -0.2 Max 85 125 155 VDDQF+0.6 2.45 3.3 14 100 100 Unit C C C V V V V mA hours
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
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M36WT864TF, M36WT864BF
DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 16, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 16. Operating and AC Measurement Conditions
SRAM Parameter Min VDD Supply Voltage VDDQ Supply Voltage VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VDDF VDDF/2 - 40 30 2 0 to VDDQ VDDQ/2 85 - 2.7 70 Max - 3.3 Flash Memory 70/ 85/ 100 Min 1.65 2.7 11.4 -0.4 - 40 30 5 Max 2.2 3.3 12.6 VDDQ+0 .4 85 V V V V C pF ns V V Units
Figure 9. AC Measurement I/O Waveform
Figure 10. AC Measurement Load Circuit
VDDQF
VDDF VDDF/2 0V VDDQF VDDF 16.7k
AI06110
Note: VDDF = VDDS
DEVICE UNDER TEST 0.1F 0.1F CL 16.7k
CL includes JIG capacitance
AI06274
Table 17. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF
Note: Sampled only, not 100% tested.
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M36WT864TF, M36WT864BF
Table 18. Flash DC Characteristics - Currents
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=40MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 Word 8 Word Continuous 4 Word Supply Current Synchronous Read (f=54MHz) Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPPF = VDD Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read in another Bank E = VDD 0.2V VPPF = VPPH VPPF = VDD VPPF = VPPH VPPF = VDD VPPF = VPPH VPPF VDD VPPF VDD 10 13 20 26 mA mA VPPF = VDD VPPF = VPPH 10 8 20 15 mA mA 8 Word Continuous IDD2 IDD3 IDD4 RP = VSS 0.2V E = VDD 0.2V E = VIL, G = VIH VPPF = VPPH IDD1 3 6 8 6 7 10 13 10 10 10 8 Min Typ Max 1 1 6 13 14 10 16 18 25 50 50 50 15 Unit A A mA mA mA mA mA mA mA A A A mA
IDD6 (1,2)
Supply Current (Dual Operations)
16
30
mA
IDD7(1)
Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program)
10 2 0.2 2 0.2 100 0.2 0.2
50 5 5 5 5 400 5 5
A mA A mA A A A A
IPP1(1) VPPF Supply Current (Erase)
IPP2 IPP3(1)
VPPF Supply Current (Read) VPPF Supply Current (Standby)
Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents.
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M36WT864TF, M36WT864BF
Table 19. Flash DC Characteristics - Voltages
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDD Lock Voltage RP pin Extended High Voltage 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1 11.4 1.8 12 1.95 12.6 0.9 Test Condition Min -0.5 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V
Table 20. SRAM DC Characteristics
Symbol IDD1 (1,2) IDD2 (3) Parameter Operating Supply Current Operating Supply Current Test Condition VDDS = 3.3V, f = 1/tAVAV, IOUT = 0mA 70ns Min Typ Max 35 4 Unit mA mA
VDDS = 3.3V, f = 1MHz, IOUT = 0mA VDDS = 3.3V, f = 0, E1 VDDS -0.2V or E2 0.2V or LB=UB VDDS -0.2V 0V VIN VDDS 0V VOUT VDDS (4) -1 -1 2.2 -0.3 IOH = -1.0mA IOL = 2.1mA 2.4 1
ISB ILI ILO VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
20 1 1 VDDS + 0.3 0.6
A A A V V V
0.4
V
Average AC current, cycling at tAVAV minimum. E1 = VIL AND E2 = VIH, LB OR/AND UB = VIL, VIN = VIL OR VIH. E1 0.2V AND E2 VDDS -0.2V, LB OR/AND UB 0.2V, VIN 0.2V OR VIN VDDS -0.2V. Output disabled.
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A0-A21 VALID VALID tAVAV tAVLH tLHAX tAXQX
LF tLLLH tLLQV tELLH tELQV tLHGL
EF tEHQZ tELQX tEHQX
GF tGLQV tGLQX tELTV tGHQX tGHQZ tEHTZ
Figure 11. Flash Asynchronous Random Access Read AC Waveforms
WAITF tAVQV
Hi-Z
DQ0-DQ15
Hi-Z
VALID
Valid Address Latch
Outputs Enabled
Data Valid
Standby
M36WT864TF, M36WT864BF
Note. Write Enable, WF, is High, WAIT is active Low.
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AI06275
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VALID ADDRESS tAVAV VALID ADDRESS VALID ADDRESS tAVLH tLHAX VALID ADDRESS VALID ADDRESS tLLLH tLLQV tELLH tLHGL tELQV tELQX tELTV tGLQV tGLQX VALID DATA tAVQV1 VALID DATA VALID DATA VALID DATA Outputs Enabled Valid Data Standby
AI06276
A2-A21
A0-A1
M36WT864TF, M36WT864BF
LF
Figure 12. Flash Asynchronous Page Read AC Waveforms
EF
GF
WAITF(1)
Hi-Z
DQ0-DQ15
Valid Address Latch
Note 1. WAIT is active Low.
M36WT864TF, M36WT864BF
Table 21. Flash Asynchronous Read AC Characteristics
Symbol tAVAV tAVQV tAVQV1 tAXQX (1) tELTV Read Timings tELQV
(2)
Alt tRC tACC tPAGE tOH
Parameter Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid Min Max Max Min Max Max Min Max Min Max Max Min Min Max Min Min Min Min Max Min
M36WT864TF/BF 70 70(3) 70(3) 20(3) 0 14(3) 70(3) 0 20(3) 0 20(3) 20 0 0 20(3) 10 10 10 10 70(3) 0 85 85 85 25 0 18 85 0 20 0 20 25 0 0 20 10 10 10 10 85 0 100 100 100 25 0 18 100 0 20 0 20 25 0 0 20 10 10 10 10 100 0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCE tLZ
Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z
tELQX (1) tEHTZ tEHQX (1) tEHQZ (1) tGLQV (2) tGLQX (1) tGHQX (1) tGHQZ (1) tAVLH
tOH tHZ tOE tOLZ tOH tDF tAVADVH tELADVH tADVHAX
Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition
Latch Timings
tELLH tLHAX tLLLH tLLQV tLHGL
tADVLADVH Latch Enable Pulse Width tADVLQV tADVHGL Latch Enable Low to Output Valid (Random) Latch Enable High to Output Enable Low
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. To be characterized.
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VALID VALID tKHQX tKHQV tKHQX VALID VALID tKHQV NOT VALID tLLLH tKHQV tKHQX tEHQX tEHQZ Note 1 tEHEL tGHQX tGLQX tGHQZ tKHTX tKHTV tKHTX tKHTV tEHTZ Note 2 Note 2 Note 2 Valid Valid Data Flow Boundary Crossing Data X Latency Standby
AI06277
DQ0-DQ15
Hi-Z
A0-A21
VALID ADDRESS
tAVLH
M36WT864TF, M36WT864BF
LF
tLLKH
tAVKH
KF
tELKH
tKHAX
Figure 13. Flash Synchronous Burst Read AC Waveforms
EF
GF
tELTV
Hi-Z
WAITF
Address Latch
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge.
DQ0-DQ15
VALID NOT VALID NOT VALID NOT VALID NOT VALID NOT VALID
Hi-Z
A0-A21
VALID ADDRESS
tAVLH tLLLH
LF tKHQV tEHQX tEHQZ Note 1 tEHEL
tLLKH
tAVKH
KF(4)
tELKH
tKHAX
Figure 14. Flash Single Synchronous Read AC Waveforms
EF tGLQX tGLQV tGHQX tGHQZ
GF tEHTZ
tELTV tKHTV Note 3
WAITF(2)
Hi-Z
M36WT864TF, M36WT864BF
Note 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode. WAIT signals valid data if the addressed bank is in Read Array mode. 4. Address latched and data output on the rising clock edge.
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AI06278
M36WT864TF, M36WT864BF
Figure 15. Flash Clock input AC Waveform
tKHKL
tKHKH
tf
tr
tKLKH
AI06981
Table 22. Flash Synchronous Read AC Characteristics
M36WT864TF/BF Symbol Alt Parameter 70 tAVKH tELKH Synchronous Read Timings tELTV tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH tKHKL tKLKH tf tr tCLKHAX tCLKHQV tAVCLKH tELCLKH Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Low to Wait Valid Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=40MHz) tCLK Clock Period (f=54MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Min Min 18.5 4.5 5 5 ns ns Min Min Max Min Max Min Max 9 9 14(3) 14(3) 20(3) 10 14(3) 85 9 9 18 14 20 10 18 100 9 9 18 14 20 10 18 ns ns ns ns ns ns ns Unit
tCLKHQX tADVLCLKH
Min Min Min
4 9
4 9 25
4 9 25
ns ns ns
Max
3
3
3
ns
Note: 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 21, Asynchronous Read AC Characteristics. 3. To be characterized.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAX tWHAV VALID ADDRESS tLHAX tLLLH
A0-A21
tAVLH
LF tWHLL
tELLH
EF tWHEH
tELWL
GF tWHWL tWHGL
tGHWL
WF tWLWH tWHEL tWHDX COMMAND CMD or DATA tWHWPL tWPHWH tQVWPL tWHQV STATUS REGISTER tELQV
tDVWH
Figure 16. Flash Write AC Waveforms, Write Enable Controlled
DQ0-DQ15
WPF tWHVPL tVPHWH tQVVPL
VPPF tELKV
KF CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI06279
M36WT864TF, M36WT864BF
SET-UP COMMAND
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M36WT864TF, M36WT864BF
Table 23. Flash Write AC Characteristics, Write Enable Controlled
M36WT864TF/BF Symbol tAVAV tAVLH tAVWH(4) tDVWH tELLH tELWL tELQV Write Enable Controlled Timings tELKV tGHWL tLHAX tLLLH tWHAV(4) tWHAX(4) tWHDX tWHEH tWHEL(2) tWHGL tWHLL tWHWL tWHQV tWLWH tQVVPL Protection Timings tQVWPL tVPHWH tWHVPL tWHWPL tWPHWH tVPS tWP tWPH tAH tDH tCH tCS tWC tDS Alt tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High Data Valid to Write Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable High to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low Write Enable High to Write Enable Low Write Enable High to Output Valid Write Enable Low to Write Enable High Output (Status Register) Valid to VPPF Low Output (Status Register) Valid to Write Protect Low VPPF High to Write Enable High Write Enable High to VPPF Low Write Enable High to Write Protect Low Write Protect High to Write Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70(3) 10 45(3) 45(3) 10 0 70(3) 9 20 10 10 0 0 0 0 25(3) 0 0 25 95(3) 45(3) 0 0 200 200 200 200 85 85 10 50 50 10 0 85 9 20 10 10 0 0 0 0 25 0 0 25 110 50 0 0 200 200 200 200 100 100 10 50 50 10 0 100 9 20 10 10 0 0 0 0 25 0 0 25 125 50 0 0 200 200 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 3. To be characterized. 4. Meaningful only if LF is always kept low.
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PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVEH tEHAX VALID ADDRESS tLHAX tLLLH
A0-A21
tAVLH
LF tELLH tEHWH
WF
tWLEL
GF tEHEL tEHGL
tGHEL
EF tELEH tEHDX COMMAND CMD or DATA tEHWPL tWPHEH tQVWPL tWHEL tWHQV tELQV
tDVEH
Figure 17. Flash Write AC Waveforms, Chip Enable Controlled
DQ0-DQ15
STATUS REGISTER
WPF tEHVPL tVPHEH tQVVPL
VPPF tELKV
KF CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING
AI06280
M36WT864TF, M36WT864BF
SET-UP COMMAND
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M36WT864TF, M36WT864BF
Table 24. Flash Write AC Characteristics, Chip Enable Controlled
M36WT864TF/BF Symbol tAVAV tAVEH tAVLH tDVEH tEHAX tEHDX Chip Enable Controlled Timings tEHEL tEHGL tEHWH tELKV tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL(2) tWHQV tWLEL tEHVPL Protection Timings tEHWPL tQVVPL tQVWPL tVPHEH tWPHEH tVPS tCS tWP tCH tDS tAH tDH tWPH Alt tWC tWC Parameter 70 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High Data Valid to Write Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Chip Enable Low to Clock Valid Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low Write Enable High to Output Valid Write Enable Low to Chip Enable Low Chip Enable High to VPPF Low Chip Enable High to Write Protect Low Output (Status Register) Valid to VPPF Low Output (Status Register) Valid to Write Protect Low VPPF High to Chip Enable High Write Protect High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 70(3) 45(3) 10 45(3) 0 0 25 0 0 9 45(3) 10 70(3) 20 10 10 25(3) 95 0 200 200 0 0 200 200 85 85 50 10 50 0 0 25 0 0 9 50 10 85 20 10 10 25 110 0 200 200 0 0 200 200 100 100 50 10 50 0 0 25 0 0 9 50 10 100 20 10 10 25 125 0 200 200 0 0 200 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 3. To be characterized.
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M36WT864TF, M36WT864BF
Figure 18. Flash Reset and Power-up AC Waveforms
WF, EF, GF, LF
tPHWL tPHEL tPHGL tPHLL
tPLWL tPLEL tPLGL tPLLL
RP tVDHPH VDD, VDDQ Power-Up Reset
AI06281
tPLPH
Table 25. Flash Reset and Power-up AC Characteristics
Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH (1,2) tVDHPH (3) Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test Condition During Program During Erase Other Conditions Min Min Min 70 10 20 80 85 10 20 80 100 10 20 80 Unit s s ns
Min
30
30
30
ns
Min Min
50 50
50 50
50 50
ns s
Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.
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M36WT864TF, M36WT864BF
Figure 19. SRAM Address Controlled, Read AC Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI05839
Note: E1S = Low, E2S = High, GS = Low, WS = High, UBS = Low and/or LBS = Low.
Figure 20. SRAM Chip Enable or Output Enable Controlled, Read AC Waveforms
tAVAV A0-A18 tAVQV tELQV E1S VALID tAXQX tEHQZ
E2S
tELQX tGLQV GS tGLQX DQ0-DQ15 tBLQV UBS, LBS tBLQX
AI06282
tGHQZ
VALID tBHQZ
Note: Write Enable (WF) = High
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M36WT864TF, M36WT864BF
Figure 21. SRAM Chip Enable or UBS/LBS Controlled, Standby AC Waveforms
E1S, UBS, LBS
E2S IDD ISB tPU 50%
AI06283
tPD
Table 26. SRAM Read and Standby AC Characteristics
M36WT864TF/BF Symbol tAVAV tAVQV tAXQX (1) tBHQZ (2,3,4) tBLQV tBLQX (1) tEHQZ (2,3,4) tELQV tELQX (1) tGHQZ (2,3,4) tGLQV tGLQX (1) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up Parameter 70 Min Max Min Max Max Min Max Max Min Max Max Min Max Min 70 70 5 25 70 5 25 70 5 25 35 5 0 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VDDS or 0.7VDDS. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M36WT864TF, M36WT864BF
Figure 22. SRAM Write AC Waveforms, Write Enable Controlled
tAVAV A0-A18 VALID tAVWH tAVEL E1S tELWH tWHAX
E2S tWLWH tAVWL WS tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLBH UBS, LBS
AI06284
tWHQX
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
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M36WT864TF, M36WT864BF
Figure 23. SRAM Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A18 VALID tAVEH tAVEL E1S tELEH tEHAX
E2S tAVWL WS tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLBH UBS, LBS
AI06285
tWLEH
Figure 24. SRAM Write AC Waveforms, UB/LB Controlled
tAVAV A0-A18 VALID tAVBH E1S tBHAX
E2S tAVWL WS tWLQZ DQ0-DQ15 DATA (1) tBHDX DATA INPUT tDVBH tAVBL UBS, LBS
AI06286
tWLBH
tBLBH
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
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M36WT864TF, M36WT864BF
Table 27. SRAM Write AC Characteristics
M36WT864TF/BF Symbol tAVAV tAVBH tAVBL tAVEH tAVEL tAVWH tAVWL tBHAX tBHDX tBLBH tBLEH tBLWH tDVBH tDVEH tDVWH tEHAX tEHDX tELBH tELEH tELWH tWHAX tWHDX tWHQX (1) tWLBH tWLEH tWLQZ (1,2,3) tWLWH Write Cycle Time Address Valid to LBS, UBS High Address Valid to LBS, UBS Low Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low LBS, UBS High to Address Transition LBS, UBS High to Input Transition LBS, UBS Low to LBS, UBS High LBS, UBS Low to Chip Enable High LBS, UBS Low to Write Enable High Input Valid to LBS, UBS High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to LBS, UBS High Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to LBS, UBS High Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 70 60 0 60 0 60 0 0 0 60 60 60 30 30 30 0 0 60 60 60 0 0 5 60 60 20 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. Tested initially and after any design or process changes that may affect these parameters.
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Figure 25. SRAM Low VDD Data Retention AC Waveforms, E1S Controlled
DATA RETENTION MODE 3.3V VDDS 2.7V
VDR > 1.5V tCDR E1S VDR - 0.2V or UBS = LBS VDR - 0.2V E1S or UBS/LBS tR
AI06287
Figure 26. SRAM Low VDD Data Retention AC Waveforms, E2S Controlled
DATA RETENTION MODE 3.3V VDDS 2.7V
VDR > 1.5V tCDR E2S 0.2V E2S tR
AI06288
Table 28. SRAM Low VDD Data Retention Characteristics
Symbol IDDDR (1) tCDR (1,2) tR (2) VDR (1) Parameter Supply Current (Data Retention) Chip Deselected to Data Retention Time Operation Recovery Time Supply Voltage (Data Retention) E1S VDDS -0.2V or E2S 0.2V or UBS = LBS VDDS -0.2V, f = 0 Test Condition VDD = 1.5V, E1S VDDS -0.2V or E2S 0.2V or UBS = LBS VDDS -0.2V, f = 0 0 tAVAV 1.5 Min Typ 5 Max 10 Unit A ns ns V
Note: 1. All other Inputs at VIH VDDS -0.2V or VIL 0.2V. 2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VDDS +0.2V.
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PACKAGE MECHANICAL Figure 27. Stacked LFBGA96 - 8x14mm, 8x10ball array, 0.8mm pitch, Bottom View Package Outline
D D1
SE E E2 E1 b BALL "A1"
e ddd
FE1 FE
FD A
SD A2 A1
BGA-Z31
Note: Drawing is not to scale.
Table 29. Stacked LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 ddd E E1 E2 e FD FE FE1 SD SE 14.000 7.200 10.400 0.800 1.200 3.400 1.800 0.400 0.400 13.900 - - - - - - - - 0.960 0.400 8.000 5.600 0.350 7.900 - 0.450 8.100 - 0.100 14.100 - - - - - - - - 0.5512 0.2835 0.4094 0.0315 0.0472 0.1339 0.0709 0.0157 0.0157 0.5472 - - - - - - - - 0.300 0.0378 0.0157 0.3150 0.2205 0.0138 0.3110 - 0.0177 0.3189 - 0.0039 0.5551 - - - - - - - - millimeters Typ Min Max 1.400 0.0118 Typ inches Min Max 0.0551
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PART NUMBERING Table 30. Ordering Information Scheme
Example: Device Type M36 = MMP (Flash + SRAM) Architecture W = Multiple Bank, Burst mode Operating Voltage T = VDDF = 1.65V to 2.2V; VDDS = VDDQF = 2.7V to 3.3V SRAM Chip Size & Organization 8 = 8 Mbit (512K x16-bit) Device Function 64T = 64 Mbit (x16), Multiple Bank, Top Boot 64B = 64 Mbit (x16), Multiple Bank, Bottom Boot B = SRAM Asynchronous 70ns Speed 70 = 70ns 85 = 85ns 10 = 100ns Package ZA = LFBGA96 - 8x14mm, 8x10 ball array, 0.8mm pitch Temperature Range 6 = -40 to 85C Option T = Tape & Reel packing M36WT864TF 70 ZA 6 T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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REVISION HISTORY Table 31. Document Revision History
Date 10-Jul-2002 Version 1.0 First Issue Revision Details
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APPENDIX A. FLASH BLOCK ADDRESS TABLES Table 32. Flash Top Boot Block Addresses
Bank # 0 1 2 3 4 Parameter Bank 5 6 7 8 9 10 11 12 13 14 15 16 17 Bank 0 18 19 20 21 22 23 24 25 Bank 1 26 27 28 29 30 31 32 33 Bank 2 34 35 36 37 38 Size (KWord) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range Bank 3 3FF000-3FFFFF 3FE000-3FEFFF 3FD000-3FDFFF 3FC000-3FCFFF 3FB000-3FBFFF 3FA000-3FAFFF 3F9000-3F9FFF 3F8000-3F8FFF Bank 4 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF Bank 5 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF Bank 6 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF Bank 7 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF
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79 80 81 Bank 8 82 83 84 85 86 87 88 89 Bank 9 90 91 92 93 94 95 96 97 Bank 10 98 99 100 101 102 103 104 105 Bank 11 106 107 108 109 110 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF Bank 14 Bank 13 Bank 12 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks.
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Table 33. Flash Bottom Boot Block Addresses
Bank # 134 133 132 Bank 14 131 130 129 128 127 126 125 124 Bank 13 123 122 121 120 119 118 117 116 Bank 12 115 114 113 112 111 110 109 108 Bank 11 107 106 105 104 103 102 101 100 Bank 10 99 98 97 96 95 Size (KWord) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Address Range Bank 9 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF Bank 8 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF Bank 7 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF Bank 6 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF Bank 5 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF
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54 53 52 Bank 4 51 50 49 48 47 46 45 44 Bank 3 43 42 41 40 39 38 37 36 Bank 2 35 34 33 32 31 30 29 28 Bank 1 27 26 25 24 23 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF Parameter Bank Bank 0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 007000-007FFF 006000-006FFF 005000-005FFF 004000-004FFF 003000-003FFF 002000-002FFF 001000-001FFF 000000-000FFF
Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks.
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APPENDIX B. FLASH COMMON FLASH INTERFACE 36, 37, 38, 40 and 1 show the addresses used to The Common Flash Interface is a JEDEC apretrieve the data. The Query data is always preproved, standardized data structure that can be sented on the lowest order data outputs (DQ0read from the Flash memory device. It allows a DQ7), the other outputs (DQ8-DQ15) are set to 0. system software to query the device to determine various electrical and timing parameters, density The CFI data structure also contains a security information and functions supported by the memarea where a 64 bit unique security number is writory. The system can interface easily with the deten (see Table 1, Security Code area). This area vice, enabling the software to upgrade itself when can be accessed only in Read mode by the final necessary. user. It is impossible to change the security numWhen the Read CFI Query Command is issued ber after it has been written by ST. Issue a Read the device enters CFI Query mode and the data Array command to return to Read mode. structure is read from the memory. Tables 34, 35, Table 34. Query Structure Overview
Offset 00h 10h 1Bh 27h P A Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Sub-section Name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Lock Protection Register Unique device Number and User Programmable OTP
80h
Security Code Area
Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 35, 36, 37, 38, 40 and 1. Query data is always presented on the lowest order data outputs.
Table 35. CFI Query Identification String
Offset 00h 01h 02h 03h 04h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Sub-section Name 0020h 8810h 8811h reserved reserved reserved 0051h 0052h 0059h 0003h 0000h offset = P = 0039h 0000h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 37) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table p = 39h NA NA Query Unique ASCII String "QRY" Manufacturer Code Device Code Reserved Reserved Reserved "Q" "R" "Y" Description Value ST Top Bottom
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Table 36. CFI Query System Interface Information
Offset 1Bh Data 0017h Description VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPPF [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPPF [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical time-out per single byte/word program = 2n s Typical time-out for quadruple word program = 2n s Typical time-out per individual block erase = 2n ms Typical time-out for full chip erase = 2n ms Maximum time-out for word program = 2n times typical Maximum time-out for quadruple word = 2n times typical Maximum time-out per individual block erase = 2n times typical Maximum time-out for chip erase = 2n times typical Value 1.7V
1Ch
0022h
2.2V
1Dh
0017h
1.7V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
00C0h 0004h 0003h 000Ah 0000h 0003h 0004h 0002h 0000h
12V 16s 8s 1s NA 128s 128s 4s NA
Table 37. Device Geometry Definition
Offset Word Mode 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh M36WT864TF 2Fh 30h 31h 32h 33h 34h 35h 38h Data 0017h 0001h 0000h 0003h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h Description Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions Region 1 Information Number of identical-size erase blocks = 007Eh+1 Region 1 Information Block size in Region 1 = 0100h * 256 byte Region 2 Information Number of identical-size erase blocks = 0007h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Reserved for future erase block region information Value 8 MByte x16 Async. 8 Byte 2 127 64 KByte 8 8 KByte NA
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Offset Word Mode 2Dh 2Eh M36WT864BF 2Fh 30h 31h 32h 33h 34h 35h 38h
Data 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h 0000h
Description Region 1 Information Number of identical-size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical-size erase block = 007Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte Reserved for future erase block region information
Value 8 8 KByte 127 64 KByte NA
Table 38. Primary Algorithm-Specific Extended Query Table
Offset (P)h = 39h Data 0050h 0052h 0049h (P+3)h = 3Ch (P+4)h = 3Dh (P+5)h = 3Eh 0031h 0030h 00E6h 0003h (P+7)h = 40h (P+8)h = 41h 0000h 0000h Major version number, ASCII Minor version number, ASCII Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Primary Algorithm extended Query table unique ASCII string "PRI" Description Value "P" "R" "I" "1" "0"
(P+9)h = 42h
0001h
Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are `0'
(P+A)h = 43h (P+B)h = 44h
0003h 0000h
Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' bit 0
Yes Yes
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Offset Data Description VDD Logic Supply Optimum Program/Erase voltage (highest performance) (P+C)h = 45h 0018h bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPPF Supply Optimum Program/Erase voltage (P+D)h = 46h 00C0h bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 12V 1.8V Value
Table 39. Protection Register Information
Offset (P+E)h = 47h (P+F)h = 48h (P+10)h = 49h (P+11)h = 4Ah (P+12)h= 4Bh Data 0001h 0080h 0000h 0003h 0004h Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region Value 1
0080h 8 Bytes 16 Bytes
Table 40. Burst Read Information
Offset (P+13)h = 4Ch Data 0003h Description Page-mode read capability bits 0-7 'n' such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. Number of synchronous mode read configuration fields that follow. Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 'n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Value 8 Bytes
(P+14)h = 4Dh (P+15)h = 4Eh
0003h 0001h
3 4
(P+16)h = 4Fh (P+17)h = 50h
0002h 0007h
8 Cont.
Table 41. Bank and Erase Block Region Information
M36WT864TF (top) Offset (P+18)h =51h Data 02h M36WT864BF (bottom) Description Offset (P+18)h =51h Data 02h Number of Bank Regions within the device
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks.
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Table 42. Bank and Erase Block Region 1 Information
M36WT864TF (top) Offset (P+19)h =52h (P+1A)h =53h (P+1B)h =54h Data 0Fh 00h 11h M36WT864BF (bottom) Description Offset (P+19)h =52h (P+1A)h =53h (P+1B)h =54h Data 01h 00h 11h Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) Number of identical banks within Bank Region 1
(P+1C)h =55h
00h
(P+1C)h =55h
00h
(P+1D)h =56h
00h
(P+1D)h =56h
00h
(P+1E)h =57h
01h
(P+1E)h =57h
02h
(P+1F)h =58h (P+20)h =59h (P+21)h =5Ah (P+22)h =5Bh (P+23)h =5Ch (P+24)h =5Dh
07h 00h 00h 01h 64h 00h
(P+1F)h =58h (P+20)h =59h (P+21)h =5Ah (P+22)h =5Bh (P+23)h =5Ch (P+24)h =5Dh
07h 00h 20h 00h 64h 00h Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved 5Eh 01 5Eh 01 Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+25)h =5Eh
01h
(P+25)h =5Eh
01h
(P+26)h =5Fh
03h
(P+26)h =5Fh
03h
(P+27)h =60h (P+28)h =61h (P+29)h =62h (P+2A)h =63h (P+2B)h =64h (P+2C)h =65h
06h 00h 00h 01h 64h 00h Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
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M36WT864TF (top) Offset Data M36WT864BF (bottom) Description Offset Data Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+2D)h =66h
01h
(P+2E)h =67h
03h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks.
Table 43. Bank and Erase Block Region 2 Information
M36WT864TF (top) Offset (P+27)h =60h (P+28)h =61h Data 01h 00h M36WT864BF (bottom) Description Offset (P+2F)h =68h (P+30)h =69h Data 0Fh Number of identical banks within bank region 2 00h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2)
(P+29)h =62h
11h
(P+31)h =6Ah
11h
(P+2A)h =63h
00h
(P+32)h =6Bh
00h
(P+2B)h =64h
00h
(P+33)h =6Ch
00h
(P+2C)h =65h
02h
(P+34)h =6Dh
01h
(P+2D)h =66h (P+2E)h =67h (P+2F)h =68h (P+30)h =69h (P+31)h =6Ah (P+32)h =6Bh
06h 00h 00h 01h 64h 00h
(P+35)h =6Eh (P+36)h =6Fh (P+37)h =70h (P+38)h =71h (P+39)h =72h (P+3A)h =73h
07h 00h 00h 01h 64h 00h Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+33)h =6Ch
01h
(P+3B)h =74h
01h
74/92
M36WT864TF, M36WT864BF
M36WT864TF (top) Offset Data M36WT864BF (bottom) Description Offset Data Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved
(P+34)h =6Dh
03h
(P+3C)h =75h
03h
(P+35)h =6Eh (P+36)h =6Fh (P+37)h =70h (P+38)h =71h (P+39)h =72h (P+3A)h =73h
07h 00h 02h 00h 64h 00h Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3D)h =76h (P+3E)h =77h Feature Space definitions Reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: nx256 = number of bytes in erase block region
(P+3B)h =74h
01h
(P+3C)h =75h
03h
(P+3D)h =76h (P+3E)h =77h
Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks.
75/92
M36WT864TF, M36WT864BF
APPENDIX C. FLASH FLOWCHARTS AND PSEUDO CODES Figure 28. Program Flowchart and Pseudo Code
Start
Write 40h or 10h
program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0x40) ; /*or writeToFlash (bank_address, 0x10) ; */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write Address & Data
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06170
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP (VPPF) Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
76/92
M36WT864TF, M36WT864BF
Figure 29. Double Word Program Flowchart and Pseudo code
Start
Write 30h
Write Address 1 & Data 1 (3)
Write Address 2 & Data 2 (3)
double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (bank_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06171
Note: 1. Status check of b1 (Protected Block), b3 (VPP (VPPF) Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
77/92
M36WT864TF, M36WT864BF
Figure 30. Quadruple Word Program Flowchart and Pseudo Code
Start
Write 56h
Write Address 1 & Data 1 (3)
quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (bank_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */
Write Address 2 & Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */
Write Address 3 & Data 3 (3)
Write Address 4 & Data 4 (3)
/*Memory enters read status state after the Program command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.b7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ;
}
AI06977
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP (VPPF) Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
78/92
M36WT864TF, M36WT864BF
Figure 31. Program Suspend & Resume Flowchart and Pseudo Code
Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Write B0h
Read Status Register
SR7 = 1 YES SR2 = 1 YES Write FFh
NO
} while (status_register.SR7== 0) ;
NO
Program Complete
if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another address
} else { writeToFlash (bank_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } } Read Data
Write D0h
Write FFh
Program Continues
AI06173
79/92
M36WT864TF, M36WT864BF
Figure 32. Block Erase Flowchart and Pseudo Code
Start erase_command ( blockToErase ) { writeToFlash (bank_address, 0x20) ; writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */
Write 20h
Write Block Address & D0h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1
NO } while (status_register.SR7== 0) ;
YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
AI06174
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
80/92
M36WT864TF, M36WT864BF
Figure 33. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */
Write 70h
Read Status Register
do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
SR7 = 1 YES SR6 = 1 YES Write FFh
NO
} while (status_register.SR7== 0) ;
NO
Erase Complete
if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/
Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock else
} { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } }
Write D0h
Write FFh
Erase Continues
Read Data
AI06175
81/92
M36WT864TF, M36WT864BF
Figure 34. Locking Operations Flowchart and Pseudo Code
Start
Write 60h
locking_operation_command (address, lock_operation) { writeToFlash (bank_address, 0x60) ; /*configuration setup*/ if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (bank_address, 0x90) ;
Write 01h, D0h or 2Fh
Write 90h
Read Block Lock States
Locking change confirmed? YES Write FFh
NO
if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/
writeToFlash (bank_address, 0xFF) ; /*Reset to Read Array mode*/ }
End
AI06176
82/92
M36WT864TF, M36WT864BF
Figure 35. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (bank_address, 0xC0) ;
Write Address & Data
writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/
Read Status Register
SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End
NO } while (status_register.SR7== 0) ;
NO
VPP Invalid Error (1, 2)
if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ;
NO
Program Error (1, 2)
if (status_register.SR4==1) /*program error */ error_handler ( ) ;
NO
Program to Protected Block Error (1, 2)
if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ;
}
AI06177
Note: 1. Status check of SR1 (Protected Block), SR3 (VPP (VPPF) Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
83/92
M36WT864TF, M36WT864BF
Figure 36. Enhanced Factory Program Flowchart
SETUP PHASE Start Write 30h Address WA1 Write PD1 Address WA1(1) VERIFY PHASE
Write D0h Address WA1
Read Status Register
Read Status Register SR0 = 0? NO SR7 = 0? YES Write PD2 Address WA2(1) NO NO
Check SR4, SR3 and SR1 for program, VPP and Lock Errors Exit PROGRAM PHASE
YES SR0 = 0? YES Write PD1 Address WA1
Read Status Register
Read Status Register
SR0 = 0? YES NO Write PDn Address WAn(1)
NO
SR0 = 0? YES Write PD2 Address WA2(1)
Read Status Register
Read Status Register
SR0 = 0? YES
NO
SR0 = 0? YES Write PDn Address WAn(1)
NO
Write FFFFh Address = Block WA1 / EXIT PHASE Read Status Register
Read Status Register
SR7 = 1? YES
NO
SR0 = 0? YES Write FFFFh Address = Block WA1 /
NO Check Status Register for Errors
End
Note 1. Address can remain Starting Address WA1 or be incremented.
AI06160
84/92
M36WT864TF, M36WT864BF
Enhanced Factory Program Pseudo Code
efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.b7==1){ /*EFP aborted for an error*/ if (status_register.b4==1) /*program error*/ error_handler(); if (status_register.b3==1) /*VPP invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.b0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.b0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.b0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.b7==0); if (status_register.b4==1) /*program failure error*/ error_handler(); if (status_register.b3==1) /*VPP invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } }
85/92
M36WT864TF, M36WT864BF
Figure 37. Quadruple Enhanced Factory Program Flowchart
SETUP PHASE Start LOAD PHASE Write PD1 Address WA1(1)
Write 75h Address WA1 FIRST LOAD PHASE Read Status Register
Write PD1 Address WA1
SR0 = 0? Read Status Register YES Write PD2 Address WA2(2) SR7 = 0? YES Read Status Register
NO
NO
Check SR4, SR3 and SR1 for program, VPP and Lock Errors
SR0 = 0? YES
NO
Exit
Write PD3 Address WA3(2)
Read Status Register
SR0 = 0? YES Write PD4 Address WA4(2)
NO
EXIT PHASE
PROGRAM AND VERIFY PHASE
Read Status Register
Write FFFFh Address = Block WA1 /
NO SR0 = 0? YES Last Page? YES NO
Check Status Register for Errors
End
Note 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block. 2.The address is only checked for the first Word of each Page as the order to program the Words is fixed so subsequent Words in each Page can be written to any address.
AI06178
86/92
M36WT864TF, M36WT864BF
Quadruple Enhanced Factory Program Pseudo Code
quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.b7==1){ /*EFP aborted for an error*/ if (status_register.b4==1) /*program error*/ error_handler(); if (status_register.b3==1) /*VPP invalid error*/ error_handler(); if (status_register.b1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.b0==1) writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.b0==1) writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.b0==1) writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.b0==1) } /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.b7==0); if (status_register.b1==1) /*program to protected block error*/ error_handler(); if (status_register.b3==1) /*VPP invalid error*/ error_handler(); if (status_register.b4==1) /*program failure error*/ error_handler(); } }
87/92
M36WT864TF, M36WT864BF
APPENDIX D. FLASH COMMAND INTERFACE STATE TABLES Table 44. Command Interface States - Modify Table, Next State
Next CI State After Command Input Erase Confirm Block Read P/E Program Program Clear Electronic Erase, Quad- Resume, Program/ Read WP DWP, Read EFP status signature, Bank Erase Status EFP Block setup QWP Setup Erase Array(2) (3,4) Setup Unlock Suspend Register Register Read CFI Setup (5) Setup (3,4) Query confirm, (3,4) EFP Confirm Quad-EFP Program Program Ready Erase Setup EFP Setup Ready Setup Setup Setup Ready (Lock Error) Ready Ready (Lock Error) OTP Busy Program Busy Program Busy Program Suspended Ready (error) Erase Busy Erase Suspended Program in Erase Suspend Erase Suspended Erase Busy Program Busy Erase Busy Erase Suspended Program Suspended Program Busy Program Suspended Ready (error) Erase Busy Erase Suspended
Current CI State
Ready Lock/CR Setup Setup OTP Busy Setup Program Busy Suspend Setup Busy Erase Suspend Setup Busy
Program in Erase Suspend Busy Program in Erase Suspend Busy Program in Erase Suspend Busy Erase Suspend EFP Busy EFP Busy (6) EFP Verify (6) Quad EFP Busy (6) Quad EFP Busy(6) Program in Erase Suspend Suspended Program in Erase Suspend Busy
Program in Erase Suspend
Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Quad EFP Setup Busy
Program in Erase Suspend Suspended
Program in Erase Suspend Suspended
Erase Suspend (Lock Error) Ready (error)
Erase Suspend (Lock Error) Ready (error)
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'.EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data.
88/92
M36WT864TF, M36WT864BF
Table 45. Command Interface States - Modify Table, Next Output
Next Output State After Command Input (6) Erase Confirm P/E Resume, Program/ QuadRead EFP Block EFP Erase Status Setup Unlock Setup Suspend Register confirm, EFP Confirm
Current CI State
Read Array(2)
Program DWP, QWP Setup
(3,4)
Block Erase, Bank Erase Setup
(3,4)
Clear status Register
(5)
Read Electronic signature, Read CFI Query
Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy Erase Busy Program/Erase Program in Erase Suspend Busy Program in Erase Suspend Suspended Array Status Register
Status Register
Status Register Status Register Output Unchanged Status Register
Output Unchanged
Array
Status Register
Output Unchanged
Status Register
Output Unchanged
Electronic Signature/ CFI
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the bank's output state.
89/92
M36WT864TF, M36WT864BF
Table 46. Command Interface States - Lock Table, Next State
Next CI State After Command Input Current CI State Lock/CR Setup(4) Lock/CR Setup OTP Setup
(4)
Block Block Lock Lock-Down Confirm Confirm
Set CR Confirm Ready
EFP Exit, Quad EFP Exit (3)
Illegal Command
(5)
P/E. C. Operation Completed N/A
Ready Lock/CR Setup OTP Setup Busy Setup Program Busy Suspend Setup Busy Erase Suspend
OTP Setup Ready OTP Busy Program Busy Program Busy Program Suspended Ready (error) Erase Busy
Ready (Lock error)
Ready (Lock error)
N/A N/A Ready N/A Ready N/A N/A Ready
Lock/CR Setup in Erase Suspend
Erase Suspended
N/A
Setup Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Setup EFP Busy Verify Setup QuadEFP Busy Erase Suspend (Lock error)
Program in Erase Suspend Busy Program in Erase Suspend Busy Program in Erase Suspend Suspended Erase Suspend Ready (error) EFP Busy (2) EFP Verify
(2)
N/A Erase Suspended N/A Erase Suspend (Lock error) EFP Busy(2) EFP Verify
(2)
N/A N/A
EFP Verify Ready
(2)
N/A Ready N/A
Quad EFP Busy Quad EFP Busy (2)
Ready
Quad EFP Busy(2)
Ready
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to `0'. EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. If the P/E.C. is active, both cycles are ignored. 5. Illegal commands are those not defined in the command set.
90/92
M36WT864TF, M36WT864BF
Table 47. Command Interface States - Lock Table, Next Output
Current CI State Lock/CR Setup(3) OTP Setup
(3)
Next Output State After Command Input Block EFP Exit, Block Lock Set CR Lock-Down Quad EFP Confirm Confirm Confirm Exit (2)
Illegal Command
(4)
P/E. C. Operation Completed
Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend OTP Busy Ready Program Busy EraseBusy Program/Erase Program in Erase Suspend Busy Program in Erase Suspend Suspended
Status Register
Output Unchanged
Status Register Status Register Output Unchanged
Array
Status Register Array Output Unchanged
Output Unchanged Output Unchanged
Status Register
Output Unchanged
Array
Output Unchanged
Output Unchanged
Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 3. If the P/E.C. is active, both cycles are ignored. 4. Illegal commands are those not defined in the command set.
91/92
M36WT864TF, M36WT864BF
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
92/92

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